1. Field of the Invention
This invention relates to a circuit for increasing the inductance of a transformer and more particularly to an inductance multiplier for use with a line circuit battery feed inductor or with an inductor used in a current sink circuit.
2. Description of the Prior Art
Inductors have traditionally been used in telephony in battery feed circuits to allow a DC current to be fed to a telephone circuit. The use of the inductor allows the current to be fed to the telephone circuit through an impedance which appears resistive at frequencies below the telephone voice band cut which exhibits a very high impedance in the voice band. This very high impedance serves to prevent the battery feed circuit from loading the voice circuit and either increasing its loss or degrading its return loss. The very high impedance in the voice band further serves to attenuate cross talk between subscribers using the same common battery and to prevent noise which may be present at the battery terminals from reaching the subscriber line.
In summary, the use of an inductor exhibiting the impedance characteristics described above in a battery feed circuit has proven to be reliable and compatible with nearly all terminal equipment. The major drawback has been the large physical size and expense of the components used therein to obtain the desired impedance characteristics. Traditionally, the circuit has been physically embodied using a transformer or relay which has had split windings coupled by a DC blocking midpoint capacitor. Because the split windings must carry significantly large DC currents, the core of the transformer must be fairly large to keep it from saturating.
There have been several electronic schemes proposed in the prior art to reduce the size of the transformer or inductor, i.e., electronically multiply the inductance. One such scheme is disclosed in U.S. Pat. No. 3,881,149 which is assigned to the same assignee as is the present invention. As disclosed therein the transformer size is reduced by multiplying its inductance by placing an electronically simulated negative inductor in parallel with a tertiary winding. Another such scheme is disclosed in U.S. Pat. No. 4,463,307 wherein what can be said to be an improved version of the circuit disclosed in the '149 patent is described.
The schemes disclosed in both the '149 and '307 patents both depend upon cancelling a portion of the inductive susceptance of the inductor or transformer in order to multiply the inductance. To do that they both require an accurate knowledge of the inductance to be multiplied. In addition, the inductor must remain temperature stable, and cannot change its inductance significantly with DC current flow therethrough, or the composite inductance may change sign or become unstable. Also as set forth in the specification of the '307 patent, the practical maximum inductance multiplier factor achieved by the circuit described therein is in the order of 5 or 6.
In contrast thereto, the multiplier circuit of the present invention allows for multiplication factors of 20 or greater to be obtained. As will be described in more detail below, it allows any inductor to be multiplied by a predictable factor as long as a stable feedback loop is maintained. It also permits the use of a physically small pot core inductor. Thus, the multiplier circuit of the present invention allows there to be provided a much larger effective inductor in a much smaller physical size than has heretofore been the case.